1. Field of the Invention
The present invention relates generally to the field of flip-flop circuits and, in preferred embodiments, to an improved D flip-flop circuit which operates at high speed with low power consumption, usable in a dual modulus prescaler.
2. Related Art
A shift register is comprised of a number of elements, such as D flip-flops, cascaded in a string so that, upon clocking, the contents contained in each stage are moved, or shifted, either one stage to the left or the right. The bits of data, either 1 or 0, are passed on in order, so that the first bit in is the first bit out. The shifting takes place upon the rising or falling edge of the clock signal. Therefore, a two-stage shift register is a memory device that comprises two memory elements or cells connected together in a chain. Each cell in the chain is capable of remembering one bit of information. As a result, a two-stage shift register delays the input data for two pulses.
A data (D) flip-flop device in a master-slave configuration is a shift register element comprised of two separate latches 10, 12 and an inverter 14, as shown in FIG. 1. The output of the inverter 14 is coupled to the clock input of the second latch to supply an inverted clock signal to the second latch 12. This type of D flip-flop has been used, for example, in a dual modulus prescaler, often found in a Phase Locked Loop (PLL) of a frequency synthesizer. A data flip-flop has only one data (D) input and, regardless of the input level, the input is transferred to the output so that the next state of the output is determined by the current state of the input. A latch memory is a form of a D flip-flop that has the ability to remember a previous input and store it until the device is either cleared or the data is called up to be read by another device. When the latch enable input signal is high, the output follows the D input, similar to a D flip-flop. In this state, the latch is said to be transparent since the output follows the input. When the latch enable input signal is low, the output does not change and the latch is said to be in latch mode.
Some conventional circuits use a D flip-flop with multiple latch memory cells in a master-slave configuration. For example, a circuit of FIG. 2 has a first and a second latch cell. Each latch cell has a switching and a memory section. In the conventional circuit of FIG. 2, the D flip-flop circuit has four transistors 101, 103, 105, 107 in the input stage, a pair of differential data input terminals 100 and 102, a clock input terminal 104, a complement clock input terminal 106, a power supply 108, a pair of current sources 110, 112, a ground level 114, a pair of master switching transistors 116, 118, a pair of slave switching transistors 120, 122, a pair of master latching transistors 124, 126, a pair of slave latching transistors 128, 130, a pair of resistors 132, 134, each one on the collector of the respective transistor 124, 126, a pair of resistors 136, 138, each one on the collector of the respective transistor 128, 130, and a pair of differential output terminals 140, 142.
The clock input terminal 104 and the complement clock input terminal 106, which jointly serve as differential clock input terminals, are connected to respective bases of the transistors 101, 107 and 103, 105, respectively. The current sources 110, 112 are connected between the emitter inputs of the transistors 101, 107 and 103, 105, respectively, and the ground level 114. The current source 110 provides bias current to the master cell and the current source 112 provides bias current to the slave cell. The power supply 108 is connected at one end of the resistors 132, 134, 136, 138. Output terminals, output 140 and its complement output 142, are connected at the bases of the transistors 130, 128, respectively. The collector of the transistor 101 is commonly connected at the emitters of the transistors 116, 118. The collector of the transistor 103 is commonly connected at the emitters of the transistors 124, 126. The collector of the transistor 105 is commonly connected at the emitters of the transistors 120, 122. The collector of the transistor 107 is commonly connected at the emitters of the transistors 128, 130. The differential data signal input terminal 100 and its complement 102 are connected at the bases of the transistors 118, 116, respectively. The collectors of the transistors 118, 116 are connected at the bases of the transistors 126, 124, respectively. The collector of the transistor 124 is connected at the base of the transistor 126, and the collector of the transistor 126 is connected at the base of the transistor 124.
In this synchronous latch mode sequential circuit of FIG. 2 synchronization is obtained using a clock signal. The two latch cells in master-slave configuration operate one with an active high clock signal and the other with an active low clock signal. The data enters master cell when the clock signal is high. When the clock signal goes low, the data moves from the master cell to the slave cell and thus to the output. Output changes only on the clock edge. When the clock input signal applied to the transistors 101, 107 is of a high level, input signal level supplied to the differential data input terminals 100, 102 is provided to the transistors 124, 126, respectively, which are in a differential stage. When the clock input signal applied to the transistors 101, 107 is of a low level, the information which has been written into the transistors 124, 126 at a time the clock input signal is of a high level is latched by the slave latch that is composed of the transistors 128, 130 and stores the data. Therefore, the information present on the data input 100, at a time the clock input signal is of a high level, goes to the output 140 whenever the clock receives a low level signal.
In the conventional circuit of FIG. 2 both switching and memory sections of the master cell and slave cell use the same amount of current from each current source 110, 112, and the circuit needs a bias current from each current source 110, 112 to be on at all times. Therefore, in this circuit current consumption is high since it does not depend on the clock frequency, but on the magnitude of the chosen bias current. Switching speed of the circuit depends on the transistors' ft, load condition, and output voltage swing. The transistor's ft can be increased using higher bias current, but once the ft peak is reached, the ft and corresponding current cannot be exceeded any more. When the circuit is used in the integrated circuit of FIG. 2, the load condition is set by the resistive load 132, 134, the collector to substrate capacitance of the transistors at the output node, and the input impedance of the slave stage memory cell. Increasing the current will increase the transistors' ft but will decrease the resistive load to keep constant the output swing, so that the cell will switch faster. However, the higher the output voltage swing, the lower the cell's switching speed. Moreover, the output voltage swing cannot be decreased too much because of the noise immunity problem.
Another conventionally known circuit, used to lower power consumption in a prescaler, is described in the scientific article entitled: "A 2 GHz, 6 mW BICMOS Frequency Synthesizer", by Turgut Aytur and Behzad Razavi, 1995, pp. 264-265 of Digest of Technical Papers, IEEE International Solid State Circuits Conference, Session 15. The technique described in the article is named "current sharing", and is implemented in a device using the current where and when it is needed. This circuit functions with a voltage supply of 3 V and may operate at voltages as low as 2.7 V. However, at 2.7 V the phase noise is high and the circuit is not usable for some applications.
Therefore, the conventional D flip-flop circuits have limited use in high speed operations because the power requirement of these circuits is high. Accordingly, there is a need in the art for an improved D flip-flop circuit which operates at high speed with low power consumption, usable in a dual modulus prescaler. There is also a need for a method for reducing the power consumption of an improved D flip-flop circuit.